1. Field of the Invention
The present invention relates to inspection systems for inspecting electronic components, and more particularly to an automatic calibration system for setting threshold levels in an inspection system.
2. Background Art
U.S. Pat. No. 4,724,378 issued Feb. 9, 1993 to Murray et al and entitled CALIBRATED AUTOMATIC TEST SYSTEM discloses a calibrated automatic test system including a test station for generating digital test function codes and a test head containing a plurality of I/O pins for connection to a device under test. Each I/O pin includes a pin electronics circuit responsive to the digital test function codes for providing test signals to the device under test. The pin electronics circuits are inexpensive CMOS IC's and lack the accuracy needed to test VLSI devices at the frequencies of interest. An external calibration unit is connected to each I/O pin and data measurements are taken which represent the performance of the CMOS IC's. The data measurements are converted to calibrated function codes representing desired data values which are then stored in correction memory circuits which respond to nominal digital test function codes and substitute in their places calibrated function codes which are then supplied to the pin electronics circuits.
U.S. Pat. No. 4,651,105 issued Mar. 17, 1987 to Inbar entitled DIGITAL PEAK DETECTING MEANS FOR A PULSE TRAIN OF ELECTRICAL SIGNALS HAVING A FREQUENCY WITHIN A KNOWN FREQUENCY BANDWIDTH describes a digital peak detecting circuit for receiving a pulse train of electrical signals having a frequency within a known frequency range and for converting the same into digital signals is shown. The digital peak detecting circuit includes an input circuit having a phased-locked loop for producing clock pulses at a frequency which is a preselected integer of the electrical signals frequency and for deriving therefrom an analog input signal. A pulse control circuit receives and counts a predetermined number of clock pulses and produces count enabling signals. A peak detecting circuit is provided which includes a comparator which has the analog input signal and a analog output signal voltage applied to the inputs thereof and which has an output coupled to the pulse control circuit. A digital counting circuit is responsive to count enabling signals by changing count direction and produces discrete digital output signals which are stored in a latch register at the time the digital counting circuit changes its count direction. A digital-to-analog converter produces the analog output signal voltage and it is applied to the comparator input for comparing the analog input signal with the analog output signal voltage and the comparator enables the digital counting circuit as long as the analog input signal is of a greater magnitude than the analog output signal voltage, and when this condition is reversed, the digital counting circuit is reversed in counting direction, and the binary value thereof is stored in the latch register.
U.S. Pat. No. 4,380,757 issued Apr. 19, 1983 to Vancsa and entitled DATA ACQUISITION SYSTEM AND ANALOG TO DIGITAL CONVERTER THEREFOR describes a system in which, from a plurality of parallel channels of communication, each including a voltage-to-frequency (V/F) converter, a central clock synchronously timed for each channel, the derivation of a train of pulses having a number of pulses representative of the magnitude of an analog signal inputted to the V/F converter. The central clock also times the multiplexing at the measuring point of either the analog input signal or a bias voltage for calibration or a voltage reference for sealing. The central processor receives the counts from each train of pulses, combines them and threats them to provide a corrected count in each channel separately. Clocking and pulsing are effected through an isolation transformer associated with each channel, to and from the central processor.
Other patents which illustrate various other testing, detecting, and digital-to-analog converting and other circuits available in the art are as follows: U.S. Pat. No. 5,053,770; 5,003,196; 4,947,169; 4,829,236; 3,891,930; and 3,824,588.